Good Things Come In...Well, You Know

02.01.2010 // Posted by: Murray Slovick // Posted in: Articles, New Technology

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Once is happenstance. Twice is coincidence. Three times means it is time to pay attention.

As we get ready for this year’s round of technical conferences and seminars nanotechnology is about to hit the Trifecta: following its inclusion in ECTC 2009 last June (“Nanotechnology and Advanced Packaging”) it’s on the agenda this year at APEC (“Special Presentation: Nanotechnology - The Unique Challenge,” February 23, the Palm Springs Convention Center) and ECA (“Impact of Advanced Nano Technology on Passive Component Developments,” March 15, New Orleans Marriott).

Maybe the boys in the research labs are telling us we should know a bit more about what’s going on in nanotechnology, which is the manipulation of matter on an atomic scale to produce new structures, materials and devices with novel properties.

Nanotechnology operates in the domain of the almost unimaginably small: 1–100 nanometers (nm), with a nanometer being one billionth of a meter, about the size of 5-10 atoms. To put this into a more everyday perspective, a semiconductor transistor gate 50 nanometers wide is about one-thousandth the width of a human hair.

What follows is a brief overview of just some of the nanotechnology applications currently being studied, many of which, before too long, will become part of the work-a-day world of electronics.

Lowering the melting point of PB-free solder

Solder pastes, a mixture of solder powders (about 90%) and a chemical flux that enables the solder mass to wet the surfaces to be joined, are commonly used in surface mount technology applications in PCB assembly. The tin/lead (Sn/Pb) solder alloys that were used in most areas of electronic packaging for a long time have largely been abandoned as RoHS regulations and other environmental measures to eliminate toxic substances have taken hold.

A variety of lead-free solder alloys can be used as replacements for tin lead solders, but in particular, tin-silver-copper (Sn/Ag/Cu) has proven popular. This mixture, as all other lead replacement solders, has a higher melting point than its leaded predecessor; overall the melting points of the Sn/Ag/Cu alloy is 30 to 40 °C higher than that of the Sn/Pb alloy, result in higher processing temperatures.

The higher melting point solder compositions can, as a result, negatively affect product reliability due to higher stresses in board assemblies as well as the need for tougher component qualification requirements--chiefly because high reflow temperatures can lead to microelectronic component damage during production. Heat-sensitive components such as capacitors as well as flash memory or sensors with nano-size features might not survive the high processing temperatures in lead-free assembly.

The big question is whether Pb-free solders can be processed so that their melting point is lowered without undermining solder joint properties. Researchers have long understood that the melting point of many materials can be dramatically reduced by decreasing their size. In theory, then, Pb-free solder materials containing nano-sized metals should lower the apparent melting points of tin, silver and copper to below 200°C.

To that end the international electronics manufacturing consortium iNEMI last year completed its Nano-Solder Project investigating the use of nano-scale particles to suppress solder reflow temperatures. Among the study’s objectives: fabricate nano-sized SAC (96.5% Sn 3% Ag 0.5% Cu) solder with a melting point below 183°C. The project demonstrated that SAC alloys could be processed to make joints below 200° C, but also concluded that nano solder development requires further formulation optimization, process development and reliability testing before these products can become mainstream.

Nanotechnology in Capacitors….

The architecture of passive components is one area with room for improvement due to the large and growing number of passives used in electronic devices such as mobile phones and portable MP3 players.

Integration of passives in packages has many potential benefits, including betterelectrical performance, higher reliability, lower cost, and expanded design options. Among the various passives, embedded capacitors is getting renewed attention as they provide the greatest potential benefit for high density and low voltage IC packaging.

However, embedded capacitors require a very high capacitance density because of inherent limits in their capacitor area. Thus, the insulating material is required to have a very high dielectric constant.

Polymer-ceramic nanocomposites are a major candidate dielectric for embedded capacitors because they combine the low processing temperature of polymers and the high dielectric constant of ceramics nanoparticles (e.g., barium titanate) producing a nanocomposite dielectric.

But for a variety of reasons, commercially available polymer-ceramic composites can only achieve a maximum dielectric constant of about 30; a high dielectric constant of from 50 to 200 is believed to be required to make the layout area small enough for embedded capacitor applications.

For power application the operating characteristics of nanocomposite capacitors require additional development to meet the energy densities, operating voltages and charge/discharge times required in power electronic apps. For example, at present the propulsion systems for hybrid electric vehicles necessitate power components and converters that are relatively large and inefficient, limiting their use. Work is underway to develop nanocomposite dielectrics that can provide the necessary specific capacitance and operating temperature capability required for use in hybrid electric vehicles in commercial and military use.

….And in Supercaps

Unlike batteries, electrostatic capacitors operate purely by physical means, storing electricity between a pair of metal electrodes, so when power is needed, they can send out their entire charge almost instantaneously. But while capacitors charge faster and longer than normal batteries, because their storage capacity is proportional to the surface area of their electrodes, even today’s most powerful capacitors hold 25 times less energy than similarly sized chemical batteries.

While standard electrolytic capacitors are measured in microfarads (one millionth of a farad), high-capacity versions called “supercapacitors” are beginning to challenge battery technologies in applications demanding quick bursts of power. Commercial supercapacitors can achieve an energy density of 6 Watt-hours per kilogram (Wh/kg), much greater than the energy density of a conventional capacitor (however, this figure also is much lower than the energy density reached by lithium-ion batteries, which have about 32 Wh/kg).

Supercapacitors use electrodes made of activated carbon, which is extremely porous and therefore has a very large surface area. Researchers have found, however, that they can cover capacitor electrodes with millions of carbon nanotubes to increase electrode surface area and thus the amount of energy that they can hold.

A carbon nanotube (CNT) is made of cylindrical carbon molecules about a nanometer across and up to a millimeter long. It is formed when atoms of carbon are made to link together into tubular shapes. CNTs are generally extremely light, strong, and resilient, are efficient heat conductors and have excellent electrical properties, notably a speed advantage with electron-mobility values higher than amorphous silicon (electron mobility is a measure of how fast current can flow). Some CNTs can be many times more electrically conductive than steel or copper.

Chip level Interconnects

Since nanotubes have higher electron mobility than copper, and can be grown much smaller, a large number of researchers are working toward using nanotubes as interconnects, the tiny wires that transport electricity and information around the chip and to other chips, for architectures below the 45-nm process node. As interconnects get smaller, copper’s resistance increases and its ability to conduct electricity declines. This means fewer electrons are able to pass through the copper successfully, and any lingering electrons manifest themselves as heat. This heat can have a negative impact on both a chip’s speed and its performance.

On top of that when CMOS technology gets to 20-30nm resolution, quantum effects such as electron tunneling lead to unacceptable leakage and a decline in reliability.

Individual carbon nanotubes can serve as conducting pathways, and due to their small size, when bulk structures are made from these nanotubes they can contain a very large number of conducting elements. Researchers are currently exploring the use of CNTs for local interconnects, those used for short distance communication (less than a clock cycle delay), and multiple clock cycle delay interconnects, used for longer distance communication to distribute clock, data and power supply across the chip. So far they have found that CNTs are highly resistant to electromigration and can support very high current densities with little performance degradation.

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