3D Packaging: No Glasses Required

03.22.2010 // Murray Slovick // New Technology

Suddenly, the third dimension is hot. 3D films such as Avatar accounted for 11% of the $10.6 billion worth of ticket sales in the U.S. last year. 2010 is also the breakout year for the commercialization of 3D for the home, with 3D-capable flat panel TVs becoming available from Panasonic, Samsung, Sony and a host of other consumer electronics manufacturers.

So, one might ask, given that "Silicon Valley" is famous the world over as a byword for technological savvy, how come chipmakers haven’t jumped all over the Z- axis bandwagon?

Ahh, but they have. Market analyst Yole Développement (Lyon, France) has identified more than 15 different 300mm 3D IC pilot lines running or currently being installed world-wide, within R&D centers, at packaging houses, CMOS foundries or within IDM fabs.

Here’s why: The transistor density of CMOS devices has been doubling every two years, in accordance with Moore's Law. However, it is becoming increasingly difficult to sustain this growth rate because designs are approaching the physical limitations of the materials. In addition, electrical interconnects are in what has been described as a wiring crisis; wiring does not scale the way transistors scale, because the width of wires is shrinking but their length is not. To solve these problems and meet future electronic system requirements the industry is turning to novel packaging architectures such as system-in-package (SiP) and, ultimately, the vertical 3D integration of chips.

While 3D packaging promises higher function density, faster clock rates and lower power dissipation, getting there will involve a new set of integration approaches, including stacked packages, silicon interposers with Through Silicon Vias (TSV) and embedding active and passive components.

These 3D integration schemes can be classified by their interconnect hierarchy. System-in-package (SiP) approaches, for example, include one or more IC chips and are based on traditional wirebond die stacks and flip chip interconnect technologies. In SiP solutions, by utilizing the third dimension integrated passive components and ICs can be stacked closer together which not only provides miniaturization but also improves electrical performance by decreasing signal distances as short vertical interconnections replace the longer interconnects found in 2D structures.

That’s good because as signal frequencies increase to several GHz in high speed digital applications, to maintain signal integrity much shorter interconnects between chips and passive components are required. Make the interconnect wires shorter, and you cut the delay time.

Early adopters already have successfully introduced 3D packaging technology in volume production for MEMS and CMOS image sensors. MEMS benefit from 3D in order to combine the device with its CMOS ASIC. With image sensors the trend is to stack the DSP chips under the image sensor chip itself. Because the market for these enhanced products is extremely spirited it will drive adoption of 3D TSVs to high volumes within the next decade, according to Yole Development, with new applications also emerging including HB-LED silicon modules and solar and power components.

The broadest adoption of SiP to date has been for stacked memory/logic devices and small modules used to integrate mixed signal devices and passives for mobile phone applications. Lots of chip stacks can be found in a cell phone, mostly involving NOR flash, NAND Flash and DRAM memory.

Simplifying board-level design by integrating discrete elements into the interconnection structure as embedded components is one of the strengths of the SiP. Yole Développement has suggested that the market for thin-film Integrated Passive Devices (IPDs) is set to grow from $615 million in 2009 to be worth just over $1 billion by 2013 and $1.8 billion two years later.

Ipdia (Caen, France), a spin-off from NXP, which, in turn, is a 2006 spin-off from Philips, has developed an IPD line called PICS (passive integration and connecting substrate) devices integrating tens to hundreds of passive components such as resistors, capacitors, inductors and Zener diodes into a single silicon die. Ipdia’s current design node features product offering a capacitance density of 250nF/mm2 (3.6 V max operating voltage) for implantable medical devices.


The most innovative technology enabling the jump from 2D to 3D chip layouts is to replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. These through silicon vias (TSV) for interconnecting stacked devices at wafer level promise significant advantages in terms of electrical performances, (signal transmission, reduced power consumption, reduced timing delays) as well as a smaller form factor.

But significant questions remain, including such basic issues as fabrication methodology; whether these vias will be formed during the wafer fabrication process or during IC packaging and assembly. In the front end CMOS process TSVs can be formed before attachment to the wafer (vias first) or as a post-CMOS process, after attachment of a thinned layer to the 3D stack (vias last).

Other bottlenecks to achieving market adoption of 3D IC with TSV interconnects include the relative immaturity of design tools and development of test procedures. Issues with thermal management also could narrow 3D IC applications as the challenge of removing the heat generated has yet to be broadly addressed.

In the long run, however, the cost for TSV manufacturing could be its biggest obstacle. Because of the complexity of the additional process steps – process costs to fabricate conductive vias are high and there is also the high capital cost of the equipment required. What is more, there is the slow etch rate of silicon, which curtails throughput, and, how to say this politely, issues of TSV reliability have not been satisfactorily resolved.

Sometimes a good idea just takes time to work, so for the next few years if there are only two silicon layers to be assembled it is generally expected to be more cost-effective to use flip-chip with wire-bonders. Industry watchers expect TSV- based 3D ICs to start to gain traction in the 2012-13 time frame.

From a technical perspective 3D integration is difficult because you are connecting chips with electrode pads that have different locations and sizes, so the pads of both stacked IC chips need to be exactly aligned. One solution is to employ a silicon interposer with redistribution interconnect layers placed between two stacked substrates and connecting them with TSVs to integrate, say, a memory chip with a logic chip.

Based on silicon or glass, 3D interposers are next generation substrate technology which aims at replacing traditional PCB laminates. This type of intermediate 3D which has sometimes been referred to as “2.5-D” is perceived as a bridge platform between today’s 2D and future 3D compositions. 3D interposer modules are already in small volume production for several MEMS applications to combine ASIC and MEMS chips.

TSV interposers provide the shortest electrical path between devices and power supply decoupling capacitors and should therefore enable very high electrical performance. Allvia, a Sunnyvale CA company that describes itself as the first TSV foundry, reports it has successfully integrated embedded capacitors on a silicon interposer and has completed reliability testing. Capacitance values higher than 1,500 nF/cm2 have been achieved for the embedded capacitors, according to Allvia.


Progress in the fabrication of through-silicon vias has opened possibilities for high-density-area array interconnects between stacked processor and memory chips. A microprocessor die, for example, might have face-down chips bonded to it for memory and graphics with vias placed through a passive silicon interposer chip and active circuit chips on either side. One challenge this sandwich creates is to remove the heat generated, and researchers are now exploring the use of cooling fluid running through microchannels in the interposer.

To that end IBM, Switzerland’s École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) recently entered into a four-year collaborative project called CMOSAIC to understand how chip cooling techniques can support a 3D chip architecture. Researchers will focus on the use of hair-thin, liquid cooling microchannels measuring only 50 microns in diameter between active chips. They plan to design these microchannels with single-phase liquid and two-phase cooling systems using nano-surfaces that pipe coolants—including water and environmentally-friendly refrigerants—within a few millimeters of the chip to absorb the heat, like a sponge, and draw it away.

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Featured Contributor:
Murray Slovick

Murray Slovick

Murray Slovick is Editorial Director of Intelligent TechContent, an editorial services company that produces technical articles, white papers and social media posts for clients in the semiconductor/electronic design industry. Trained as an engineer, he has more than 20 years of experience as chief editor of award-winning publications covering various aspects of consumer electronics and semiconductor technology. He previously was Editorial Director at Hearst Business Media where he was responsible for the online and print content of Electronic Products, among other properties in the U.S. and China. He has also served as Executive Editor at CMP’s eeProductCenter and spent a decade as editor-in-chief of the IEEE flagship publication Spectrum.

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